Semiconductor device including a Fin-FET and method of manufacturing the same

ABSTRACT

A semiconductor device includes a field effect transistor (FET). The FET includes a channel region and a source/drain region disposed adjacent to the channel region. The FET also includes a gate electrode disposed over the channel region. The FET is an n-type FET and the channel region is made of Si. The source/drain region includes an epitaxial layer including Si 1-x-y M1 x M2 y , where M1 is one or more of Ge and Sn, and M2 is one or more of P and As, and 0.01≤x≤0.1.

TECHNICAL FIELD

The disclosure relates to method of manufacturing semiconductor integrated circuits, and more particularly to method of manufacturing semiconductor devices including fin field effect transistors (FinFETs), and semiconductor devices.

BACKGROUND

As the semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs, challenges from both fabrication and design issues have resulted in the development of three-dimensional designs, such as a fin field effect transistor (Fin FET) and the use of a metal gate structure with a high-k (dielectric constant) material. The metal gate structure is often manufactured by using gate replacement technologies, and sources and drains are formed by using an epitaxial growth method.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 illustrates experimental results of various epitaxial layers for a source/drain region of an n-type field effect transistor in accordance with embodiments of the present disclosure.

FIGS. 2A and 2B illustrate experimental results showing Ge concentration effects on electrical properties.

FIGS. 3A, 3B and 3C illustrate one of the various stages in a semiconductor device fabrication process in accordance with embodiments of the present disclosure.

FIGS. 4A, 4B and 4C illustrate one of the various stages in a semiconductor device fabrication process in accordance with embodiments of the present disclosure.

FIGS. 5A, 5B and 5C illustrate one of the various stages in a semiconductor device fabrication process in accordance with embodiments of the present disclosure.

FIGS. 6A, 6B and 6C illustrate one of the various stages in a semiconductor device fabrication process in accordance with embodiments of the present disclosure.

FIGS. 7A, 7B and 7C illustrate one of the various stages in a semiconductor device fabrication process in accordance with embodiments of the present disclosure.

FIGS. 8A, 8B and 8C illustrate one of the various stages in a semiconductor device fabrication process in accordance with embodiments of the present disclosure.

FIGS. 9A, 9B and 9C illustrate one of the various stages in a semiconductor device fabrication process in accordance with embodiments of the present disclosure.

FIGS. 10A, 10B and 10C illustrate one of the various stages in a semiconductor device fabrication process in accordance with embodiments of the present disclosure.

FIGS. 11A, 11B and 11C illustrate one of the various stages in a semiconductor device fabrication process in accordance with embodiments of the present disclosure.

FIGS. 12A, 12B and 12C illustrate one of the various stages in a semiconductor device fabrication process in accordance with embodiments of the present disclosure.

FIGS. 13A, 13B and 13C illustrate one of the various stages in a semiconductor device fabrication process in accordance with embodiments of the present disclosure.

FIGS. 14A, 14B and 14C illustrate one of the various stages in a semiconductor device fabrication process in accordance with embodiments of the present disclosure.

FIGS. 15A, 15B and 15C illustrate one of the various stages in a semiconductor device fabrication process in accordance with embodiments of the present disclosure.

FIGS. 16A, 16B and 16C illustrate one of the various stages in a semiconductor device fabrication process in accordance with embodiments of the present disclosure.

FIGS. 17A, 17B and 17C illustrate one of the various stages in a semiconductor device fabrication process in accordance with embodiments of the present disclosure.

FIGS. 18A, 18B, 18C and 18D illustrate one of the various stages in a semiconductor device fabrication process in accordance with embodiments of the present disclosure.

FIGS. 19A, 19B and 19C illustrate one of the various stages in a semiconductor device fabrication process in accordance with embodiments of the present disclosure.

FIGS. 20A, 20B and 20C illustrate one of the various stages in a semiconductor device fabrication process in accordance with other embodiments of the present disclosure.

FIGS. 21A, 21B and 21C illustrate one of the various stages in a semiconductor device fabrication process in accordance with other embodiments of the present disclosure.

FIGS. 22A, 22B and 22C illustrate one of the various stages in a semiconductor device fabrication process in accordance with other embodiments of the present disclosure.

DETAILED DESCRIPTION

It is to be understood that the following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, dimensions of elements are not limited to the disclosed range or values, but may depend upon process conditions and/or desired properties of the device. Moreover, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed interposing the first and second features, such that the first and second features may not be in direct contact. Various features may be arbitrarily drawn in different scales for simplicity and clarity. In the accompanied drawings, some layers/features may be omitted for simplification.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. In addition, the term “made of” may mean either “comprising” or “consisting of.” Further, in the following fabrication process, there may be one or more additional operations in/between the described operations, and the order of operations may be changed.

Disclosed embodiments relate to methods and structures of forming source/drain (S/D) structures for fin field-effect transistors (FinFETs), in particular for n-type FinFETS. The embodiments such as those disclosed herein are generally applicable not only to FinFETs but also to a planar type FET, a double-gate, surround-gate, omega-gate or gate-all-around transistor, a 2-dimensional FET and/or a nanowire transistor, or any suitable device having source/drain epitaxial regions.

In order to achieve high-operational speed devices, carrier mobility in a channel region of an FET can be increased by applying appropriate stress to a crystalline semiconductor material in the channel region. As one technique to apply the stress, a crystalline semiconductor material having a different lattice constant than the channel region is provided at a source/drain region of the FET. A crystalline semiconductor material having a smaller lattice constant than the channel region is used in the source/drain (S/D) region of an n-type FET to apply tensile stress to the channel region. For example, SiP, SiC and/or SiCP are used for the S/D region of an n-type FET, where the channel region is made of silicon. On the other hand, a crystalline semiconductor material having a larger lattice constant than the channel region is used in the S/D region of a p-type FET to apply compressive stress to the channel region. For example, SiGe and/or Ge are used for the source/drain (S/D) region of a p-type FET, where the channel region is made of silicon. The crystalline semiconductor material for the S/D region is formed by an epitaxial growth method. In this disclosure, the term “source/drain” or “S/D” refers to a source and/or a drain and the source and the drain have substantially the same structure with each other.

In the present disclosure, the inventors found that adding Ge in a SiP S/D epitaxial region can increase material thermal stability and improve electrical properties of the S/D regions for an n-type FET.

For example, after the S/D epitaxial layers are formed, subsequent manufacturing operations including various thermal operations are performed to manufacture a semiconductor device. Such thermal operations, however, decrease the number of active carriers in the S/D regions, thereby increasing contact resistance between the S/D region and an S/D contact metal. However, as shown below, the incorporation of Ge in the SiP epitaxial layer can release the local lattice stress more than an SiP epitaxial layer without Ge, and can have more stable P binding energy than in the SiP epitaxial layer without Ge. Accordingly, it is possible to increase the thermal stability of the S/D epitaxial layer. In addition, the SiP epitaxial layer including Ge (herein after may be referred to as “SiGeP”) can have a higher P (phosphorous) activation rate (greater number of activated P atoms) than the SiP epitaxial layer without Ge after the thermal operations.

FIG. 1 illustrates experimental results of various epitaxial layers for a source/drain region of an n-type field effect transistor in accordance with embodiments of the present disclosure. In FIG. 1, the samples including SiP and SiGeP epitaxial layers were prepared and the active phosphorous concentration and mobility of electrons were measured after various thermal operations. In Conditions #3 and #4, Ge was introduced during an epitaxial growth of SiP and in Condition #5, Ge was introduced by ion implantation after the SiP epitaxial growth.

As shown in FIG. 1, when Ge is included in the SiP epitaxial layer, the number of the active phosphorous becomes about 10 (ten) times or greater than the condition without Ge (compare Conditions #1 and #2 with Conditions #3 and #4). Further, FIG. 1 shows that even though Ge, which is a larger element in size than Si and would reduce the stress caused by SiP, is included, the mobility does not substantially change. Generally, when the phosphorous concentration increases, the mobility decreases. However, by including Ge into SiP, higher active phosphorous concentrations were obtained at higher P concentration in SiP without sacrificing the mobility. It is noted that when Ge is introduced by ion implantation, a similar increase in the number of active phosphorous was not obtained.

FIGS. 2A and 2B illustrate experimental results showing Ge concentration effects on electrical properties. In FIGS. 2A and 2B, the concentration of P is 2.0×10²¹ cm⁻³ and thickness of the SiP (or SiGeP) epitaxial layer is 50 nm, and the thermal operations same as those in Conditions #1 and #3 are performed. Ge is introduced during the epitaxial growth of the SiP layer. Two different pre-amorphization implantation (PAIs) are performed. In FIGS. 2A and 2B, the concentration of Ge in SiGeP changes from 0.5×10²¹ cm⁻³ to 4.0×10²¹ cm⁻³ (0.5×10²¹ cm⁻³, 1.0×10²¹ cm⁻³ to, 2.0×10²¹ cm⁻³ and 4.0×10²¹ cm⁻³). When SiGeP is expressed by Si_(1-x-y)Ge_(x)P_(y), and the concentration Ge corresponds to about 0.01≤x≤about 0.1. In some embodiments, the Ge amount is smaller than the P amount. In other embodiments, the Ge amount is larger than the P amount.

As shown in FIG. 2A, when Ge is not included, the resistivity of the SiP epitaxial layer is about 0.45 mΩ·cm, and when Ge is included in SiP (e.g., about 0.01≤x≤about 0.1), the resistivity of SiGeP epitaxial layer is reduced to about 0.35 mΩ·cm. Further, in FIG. 2B, when Ge is not included, the de-activation rate of P in the SiP epitaxial layer is about 25%, and when Ge is included in SiP (e.g., about 0.01≤x≤about 0.1), the de-activation rate of P in the SiGeP epitaxial layer is reduced to about 10-15%. Instead of or in addition to Ge, Sn can be included in SiP. Instead of or in addition to P, As can be included.

FIGS. 3A-19C illustrate various processes in a semiconductor device fabrication process in accordance with some embodiments of the present disclosure. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements. In FIGS. 3A-19C, the “A” figures (e.g., FIGS. 3A, 4A, etc.) illustrate a perspective view, the “B” figures (e.g., FIGS. 3B, 4B, etc.) illustrate a cross-sectional view along the Y direction corresponding to line Y1-Y1 illustrated in FIG. 3A, and the “C” figures (e.g., FIG. 3C, 4C, etc.) illustrate a cross-sectional view along the X direction corresponding to line X1-X1 illustrated in in FIG. 3A. It is understood that additional operations can be provided before, during, and after the processes shown by FIGS. 3A-19C, and some of the operations described below can be replaced or eliminated, for additional embodiments of the method. The order of the operations/processes may be interchangeable. The entire contents of U.S. patent application Ser. No. 15/620,063 are incorporated herein by reference.

Referring first to FIGS. 3A-3C, FIGS. 3A-3C illustrate the structure after dummy gate structures are formed. In FIGS. 3A-3C, there is shown a substrate 101 having one or more fin structures, with two fin structures 102 being illustrated. It is understood that two fin structures are illustrated for purposes of illustration, but other embodiments may include any number of fin structures. In some embodiments, one or more dummy fin structures are formed adjacent to the fin structure for an active FinFET. The fin structure 102 extends in the X direction and protrudes from the substrate in the Z direction, while the gate 130 extends in the Y direction.

The substrate 101 may comprise various doped regions depending on design requirements (e.g., p-type substrate or n-type substrate). In some embodiments, the doped regions may be doped with p-type or n-type dopants. For example, the doped regions may be doped with p-type dopants, such as boron or BF₂; n-type dopants, such as phosphorus or arsenic; and/or combinations thereof. The doped regions may be configured for an n-type FinFET, or alternatively configured for a p-type FinFET.

In some embodiments, the substrate 101 may be made of a suitable elemental semiconductor, such as silicon, diamond or germanium; a suitable alloy or compound semiconductor, such as Group-IV compound semiconductors (silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), GeSn, SiSn, SiGeSn), Group III-V compound semiconductors (e.g., gallium arsenide, indium gallium arsenide InGaAs, indium arsenide, indium phosphide, indium antimonide, gallium arsenic phosphide, or gallium indium phosphide), or the like. Further, the substrate 101 may include an epitaxial layer (epi-layer), which may be strained for performance enhancement, and/or may include a silicon-on-insulator (SOI) structure.

The fin structure 102 may be formed using, for example, a patterning process to form trenches such that a trench is formed between adjacent fin structures 102. As discussed in greater detail below, the fin structure 102 will be used to form a FinFET.

Isolation regions, such as shallow trench isolations (STI) 105, are disposed in the trenches over the substrate 101. Prior to forming the isolation insulating layer 105, one or more liner layers are formed over the substrate 101 and sidewalls of the bottom part 103 of the fin structures 102 in some embodiments. In some embodiments, the liner layers includes a first fin liner layer 106 formed on the substrate 101 and sidewalls of the bottom part 103 of the fin structures 102, and a second fin liner layer 108 formed on the first fin liner layer 106. Each of the liner layers has a thickness between about 1 nm and about 20 nm in some embodiments.

In some embodiments, the first fin liner layer 106 includes silicon oxide and has a thickness between about 0.5 nm and about 5 nm, and the second fin liner layer 108 includes silicon nitride and has a thickness between about 0.5 nm and about 5 nm. The liner layers may be deposited through one or more processes such as physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD), although any acceptable process may be utilized.

The isolation insulating layer 105 may be made of suitable dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectrics such as carbon doped oxides, extremely low-k dielectrics such as porous carbon doped silicon dioxide, a polymer such as polyimide, combinations of these, or the like. In some embodiments, the isolation insulating layer 105 is formed through a process such as CVD, flowable CVD (FCVD), or a spin-on-glass process, although any acceptable process may be utilized. Subsequently, portions of the isolation insulating layer 105 extending over the top surfaces of the fin structures 102, and portions of the liner layers over the top surfaces of the fin structures 102 are removed using, for example, an etch process, chemical mechanical polishing (CMP), or the like.

In some embodiments, the isolation insulating layer 105 and the liner layers are recessed to expose the upper portion 104 of the fin structure 102 as illustrated in FIGS. 3A-3C. In some embodiments, the isolation insulating layer 105 and the liner layers are recessed using a single etch processes, or multiple etch processes. In some embodiments in which the isolation insulating layer 105 is made of silicon oxide, the etch process may be, for example, a dry etch, a chemical etch, or a wet cleaning process. For example, the chemical etch may employ fluorine-containing chemical such as dilute hydrofluoric (dHF) acid. After the fin formation process, the fin height H_(fin) is about 30 nm or higher, such as about 50 nm or higher, in some embodiments. In one embodiment, the fin height is between about 40 nm and about 80 nm. It is understood that the fin height may be modified by subsequent processing. Other materials, processes, and dimensions may be used.

After the fin structure 102 is formed, a dummy gate structure including a dummy gate dielectric layer 91 and a dummy gate electrode 90 are formed over the exposed fin structure 102. The dummy gate dielectric layer 91 and the dummy gate electrode 90 will be subsequently used to define and form the source/drain regions. In some embodiments, the dummy gate dielectric layer 91 and the dummy gate electrode 90 are formed by depositing and patterning a dummy dielectric layer formed over the exposed fin structures 102 and a dummy electrode layer over the dummy gate dielectric layer. The dummy dielectric layer may be formed by thermal oxidation, CVD, sputtering, or any other methods known and used in the art for forming a dummy dielectric layer. In some embodiments, the dummy dielectric layer 91 may be made of one or more suitable dielectric materials such as silicon oxide, silicon nitride, SiCN, SiON, and SiN, low-k dielectrics such as carbon doped oxides, extremely low-k dielectrics such as porous carbon doped silicon dioxide, a polymer such as polyimide, the like, or a combination thereof. In one embodiment, SiO₂ is used.

In some embodiments, the dummy electrode layer 90 is a conductive material and may be selected from a group comprising amorphous silicon, poly silicon, amorphous germanium, poly germanium, amorphous silicon-germanium, poly silicon-germanium, metallic nitrides, metallic silicides, metallic oxides, and metals. The dummy electrode layer may be deposited by PVD, CVD, sputter deposition, or other techniques known and used in the art for depositing conductive materials. Other materials, conductive and non-conductive, may be used. In one embodiment, poly-Si is used.

A mask pattern may be formed over the dummy electrode layer to aid in the patterning. In some embodiments, a hard mask pattern including a first layer 80 and a second layer 82 is formed over a blanket layer of polysilicon. The hard mask pattern is made of one or more layers of SiO₂, SiCN, SiON, Al₂O₃, SiN, or other suitable materials. In certain embodiments, the first layer 80 includes silicon nitride (SiN) and the second layer 82 includes silicon oxide. By using the mask pattern as an etching mask, the dummy electrode layer is patterned into the dummy gate electrode 90. In some embodiments, the dummy dielectric layer 91 is also patterned to define the dummy gate dielectric layer.

Subsequently, sidewall spacers 134 are formed along sidewalls of the dummy gate structure. The sidewall spacers 134 may be formed by depositing and anisotropically etching an insulating layer deposited over the dummy gate structures, the fin structure 102, and the isolation insulating layer 105. In some embodiments, the sidewall spacers 134 are formed of silicon nitride, and have a single-layer structure. In alternative embodiments, the sidewall spacers 134 may have a composite structure including a plurality of layers. For example, the sidewall spacers 134 include a silicon oxide layer and a silicon nitride layer over the silicon oxide layer. Other materials, such as SiO₂, SiCN, SiON, SiN, SiOCN, other low k material, or combinations thereof, may also be used. The thickness of the sidewall spacer 134 is in a range from about 5 nm to about 40 nm in some embodiments.

After the dummy gate structure and the sidewall spacers are formed, source/drain (S/D) structures 120 and 121 are formed on exposed portions 104 of the fin structures 102 along opposing sides of the dummy gate structure, as shown in FIGS. 4A-4C. The S/D structures 120 and 121 may be epitaxially formed on the side faces and the top face of the exposed fin structure 104. In some embodiments, the fin structure 104 may be recessed and the S/D structure is epitaxially formed on the exposed portion of the recessed fin. The use of epitaxial grown materials in the source/drain regions allows for the source/drain regions to exert stress in a channel of a FinFET. When the S/D structures 120 and 121 are for different conductivity type FETs, the S/D structure 120 is formed while the fin structure for the S/D structure 121 is covered by a protective layer made of, for example, SiN, and then the S/D structure 121 is formed while the formed S/D structure 120 is covered by a protective layer. In one embodiment, the S/D structure 120 is for an n-type FinFET and the S/D structure 121 is for a p-type FinFET.

The materials used for the S/D structures 120 and 121 may be varied for n-type and p-type FinFETs, such that one type of material is used for the n-type FinFETs to exert a tensile stress in the channel region and another type of material for the p-type FinFETs to exert a compressive stress.

For the n-type FinFET, the S/D structure 120 includes an epitaxial layer including Si_(1-x-y)M1_(x)M2_(y), where M1 is one or more of Ge and Sn, and M2 is one or more of P and As, and about 0.01≤x≤about 0.1 (about 1 to about 10 mol %) and about 0.01≤y≤about 0.1. In certain embodiments, x is smaller than y. In other embodiments, x is larger than y. In some embodiments, as set forth above, Si_(1-x-y)Ge_(x)P_(y), where about 0.01≤x≤about 0.1 (about 1 to about 10 mol %) and about 0.01≤y≤about 0.1, is formed as the S/D structure 120, when the fin structure 104 is made of Si. In other embodiments, about 0.01≤x≤0.05. Moreover, the S/D structure 120 in some embodiments include Si_(1-x-y)Ge_(x)As_(z), where about 0.01≤x≤about 0.1 (about 1 to about 10 mol %) and about 0.01≤z≤about 0.1. Further, in other embodiments, the S/D structure 120 includes Sn instead of Ge or together with Ge, for example, SiGeSnP, SiGeSnAs, SiSnP, SiGePAs, SiSnAs or SiGeSnPAs. In such a case, the total amount of Sn and Ge is in a range from about 1 to about 10 mol %. In certain embodiments, carbon (C) is further included in the S/D structure 120.

In some embodiments, the S/D structure 120 includes two or more epitaxial layers with different composition and/or different dopant concentrations. In some embodiments, the Ge (and/or Sn) concentration in SiGeP of the S/D structures 120 increases as the distance from the fin structure 104 increases. The Ge (and/or Sn) concentration in a region closer to the fin structure 104 is smaller than that in a region closer to the outer surface of the S/D structure 120. The Ge (and/or Sn) concentration can gradually change or change in a stepwise manner.

For a p-type FET, SiGe or Ge may be used as the S/D structure 121 to form p-type FinFETs. In some embodiments, boron (B) is included in the S/D structure 121. In some embodiments, the S/D structure 121 includes two or more epitaxial layers with different compositions and/or different dopant concentrations.

As shown in FIGS. 4A and 4B, in some embodiments, the cross sections of the S/D structures 120 and/or 121 in the Y direction have substantially a hexagonal shape, and in other embodiments, the cross sections of the S/D structures 120 and/or 121 has a diamond shape, a pillar shape or a bar shape. The width W_(SD) of the S/D structure in the Y direction is in a range from about 25 nm to about 100 nm in some embodiments. The thickness W_(EPI) of the S/D structure in the Y direction is in a range from about 2 nm to about 10 nm in some embodiments.

After the S/D structures 120 and 121 are formed, as shown in FIGS. 5A-5C, a first insulating layer 122 as a liner layer or a contact etch stop layer (CESL) is deposited to cover the S/D structures 120 and 121 and on the sidewalls spacers of the dummy gate structure. The first insulating layer 122 acts as an etch stop during the patterning of a subsequently formed dielectric material. In some embodiments, the first insulating layer 122 includes SiO₂, SiCN, SiON, SiN and other suitable dielectric materials. In one embodiment, SiN is used. The first insulating layer 122 may be made of a plurality of layers that comprises combinations of the above mentioned materials. The first insulating layer 122 may be deposited through one or more processes such as PVD, CVD, or ALD, although any acceptable process may be utilized. Other materials and/or processes may be used. In some embodiments, the first insulating layer 122 has a thickness between about 0.5 nm and about 10 nm. Other thicknesses may be used in other embodiments.

After the first insulating layer 122 is formed, a first sacrificial layer 115 is formed over the first insulating layer 122, as shown in FIGS. 6A-6C. In some embodiments, the first sacrificial layer 115 includes one or more layers of silicon based dielectric material, such as SiO₂, SiCN, SiON, SiOC, SiOH, SiN, or other suitable dielectric materials. In some embodiments, the first sacrificial layer 115 is formed through a film forming process, such as, CVD, PVD, ALD, FCVD, or a spin-on-glass process, although any acceptable process may be utilized. Subsequently, portions of the first insulating layer 122 are removed using, for example, an etch process, CMP, or the like, to expose the upper surface of the dummy gate electrode.

Subsequently, the first sacrificial layer 115 is partially recessed to a level of the middle portion of the dummy gate electrode 90 in the Z direction, thereby forming openings 116, as shown in FIGS. 7A-7C. The first sacrificial layer 115 can be recessed by an etch-back process and/or wet etching. The remaining thickness of the recessed first sacrificial layer 115 is in a range from about 40 nm to about 200 nm in some embodiments.

The openings 116 are filled with an insulating material, thereby forming a mask layer 95, as shown in FIGS. 8A-8C. In some embodiments, the mask layer 95 is made of one or more layers of SiOC, SiC, SiON, SiCN, SiOCN, SiN and/or SiO₂. In one embodiment, SiN is used. The mask layer 95 may be deposited through one or more processes such as PVD, CVD, or ALD, although any acceptable process may be utilized. A planarization operation, such as, an etch-back process or CMP, may be performed to planarize the upper surface of the mask layer 95 and hard mask layer 80, as shown in FIGS. 9A-9C. By the planarization operation, the hard mask layer 80 are removed, and the upper surface of the dummy gate electrode layer 90 is exposed.

Subsequently, the dummy gate electrode 90 and the dummy gate dielectric layer 91 are removed, as shown in FIGS. 10A-10C. The removal process may include one or more etch processes. For example in some embodiments, the removal process includes selectively etching using either dry or wet etching. When dry etching is used, the process gas may include CF₄, CHF₃, NF₃, SF₆, Br₂, HBr, Cl₂, or combinations thereof. Diluting gases such as N₂, O₂, or Ar may optionally be used. When wet etching is used, the etching solution (etchant) may include NH₄OH:H₂O₂:H₂O (APM), NH₂OH, KOH, HNO₃:NH₄F:H₂O, and/or the like. The dummy gate dielectric layer may be removed using a wet etch process, such as a diluted HF acid. Other processes and materials may be used.

After the dummy gate structure is removed, a metal gate structure is formed as shown in FIGS. 11A-11C. A gate dielectric layer 131 is formed over a channel region of the fin structure 102. In some embodiments, the gate dielectric layer 131 includes one or more high-k dielectric layers (e.g., having a dielectric constant greater than 3.9). For example, the one or more gate dielectric layers may include one or more layers of a metal oxide or a silicate of Hf, Al, Zr, combinations thereof, and multi-layers thereof. Other suitable materials include La, Mg, Ba, Ti, Pb, Zr, in the form of metal oxides, metal alloy oxides, and combinations thereof. Exemplary materials include MgO_(x), BaTi_(x)O_(y), BaSr_(x)Ti_(y)O_(z), PbTi_(x)O_(y), PbZr_(x)Ti_(y)O_(z), SiCN, SiON, SiN, Al₂O₃, La₂O₃, Ta₂O₃, Y₂O₃, HfO₂, ZrO₂, HfSiON, YGe_(x)O_(y), YSi_(x)O_(y) and LaAlO₃, and the like. The formation methods of gate dielectric layer 131 include molecular-beam deposition (MBD), ALD, PVD, and the like. In some embodiments, the gate dielectric layer 131 has a thickness of about 0.5 nm to about 5 nm. In some embodiments, the gate dielectric layer 131 is formed also on sides of the sidewall spacers 134.

In some embodiments, an interfacial layer (not shown) is formed over the channel region 104 prior to forming the gate dielectric layer 131, and the gate dielectric layer 131 is formed over the interfacial layer. The interfacial layer helps buffer the subsequently formed high-k dielectric layer from the underlying semiconductor material. In some embodiments, the interfacial layer is a chemical silicon oxide, which may be formed by chemical reactions. For example, a chemical silicon oxide may be formed using deionized water+ozone (DIO₃), NH₄OH+H₂O₂+H₂O (APM), or other methods. Other embodiments utilize a different material or processes for the interfacial layer. In an embodiment, the interfacial layer has a thickness of about 0.2 nm to about 1 nm.

After the gate dielectric layer 131 is formed, a gate electrode 130 is formed over the gate dielectric layer 131. The gate electrode 130 may be a metal selected from a group of W, Cu, Ti, Ag, Al, TiAl, TiAlN, TaC, TaCN, TaSiN, Mn, Co, Pd, Ni, Re, Ir, Ru, Pt, and Zr. In some embodiments, the gate electrode 130 includes a metal selected from a group of TiN, WN, TaN, and Ru. Metal alloys such as Ti—Al, Ru—Ta, Ru—Zr, Pt—Ti, Co—Ni and Ni—Ta may be used and/or metal nitrides such as WN_(x), TiN_(x), MoN_(x), TaN_(x), and TaSi_(x)N_(y) may be used. In some embodiments, the gate electrode 130 has a thickness in the range of about 5 nm to about 100 nm. The gate electrode 130 may be formed using a suitable process such as ALD, CVD, PVD, plating, or combinations thereof. A planarization process, such as a CMP, may be performed to remove excess materials.

In certain embodiments of the present disclosure, the gate electrode 130 includes one or more work function adjustment layers (not shown) disposed on the gate dielectric layer 131. The work function adjustment layer is made of a conductive material such as a single layer of TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi or TiAlC, or a multilayer of two or more of these materials. For the n-channel FinFET, one or more of TaN, TaAlC, TiN, TiC, Co, TiAl, HfTi, TiSi and TaSi is used as the work function adjustment layer, and for the p-channel FinFET, one or more of TiAlC, Al, TiAl, TaN, TaAlC, TiN, TiC and Co is used as the work function adjustment layer.

Then, the gate electrode 130, the gate dielectric layer 131 and the work function adjustment layer are recessed, as shown in FIGS. 12A-12C, and a gate cap layer 132 is formed on the recessed gate electrode 130, as shown in FIGS. 13A-13C. In some embodiments, when the gate electrode 130 is mainly made of W, the gate electrode may be recessed using, for example, dry etch process using Cl₂/O₂/BCl₃, at a temperature range of 24° C. to 150° C., and at a pressure of below 1 Torr.

After recessing the gate electrode 130, the gate cap layer 132 is formed in the recess to protect the gate electrode 130 during subsequent processes, as shown in FIGS. 13A-13C. In some embodiments, the gate cap layer 132 includes SiO₂, SiCN, SiON, SiN, Al₂O₃, La₂O₃, SiN, a combination thereof, or the like, but other suitable dielectric films may be used. The gate cap layer 132 may be formed using, for example, CVD, PVD, spin-on, or the like. Other suitable process steps may be used. A planarization process, such as a CMP, may be performed to remove excess materials.

Then, as shown in FIGS. 14A-14C, the first sacrificial layer 115 is at least partially removed from both side regions of the S/D structures 120 and 121, to form openings 116. In some embodiments, the entire first sacrificial layer 115 is removed. The first sacrificial layer 115 may be removed by suitable etching operations, such as dry etching and/or wet etching. The etching operation substantially stops at the first insulating layer 122. In some embodiments, the first insulating layer 122 has a thickness between about 0.5 nm and about 10 nm.

As shown in FIGS. 15A-15C, after the openings 116 are formed, a second sacrificial layer 140 is formed in the openings 116. The second sacrificial layer 140 is made of a material having a higher (e.g., 5 or more) etching selectivity with respect to the materials of the first insulating layer 122 and/or the isolation insulating layer 105. In some embodiments, the second sacrificial layer 140 is made of one or more layers of Group IV elemental or compound materials, such as Si, SiGe, SiC, Ge, SiGeC and GeSn, which may be crystalline, polycrystalline or amorphous and may be doped or un-doped. In other embodiments, the second sacrificial layer 140 is made of one or more silicon based dielectric layers of SiOC, SiC, SiON, SiCN, SiOCN, SiN and/or SiO₂. Aluminum based dielectric materials, such as aluminum oxide, aluminum oxy-carbide and aluminum oxy-nitride may be used. A SOC (spin-on-carbon) may also be used. In certain embodiments, the second sacrificial layer 140 is made of one or more layers of Group III-V compound semiconductors including, but not limited to, GaAs, GaN, InGaAs, InAs, InP, InSb, InAsSb, AlN and/or AlGaN. The second sacrificial layer 140 may be deposited through one or more processes such as PVD, CVD, or ALD, although any acceptable process may be utilized. Other materials and/or processes may be used. In one embodiment, amorphous or poly Si is used as the second sacrificial layer 140. In other embodiments, amorphous or poly Si_(1-x)Ge_(x), where x is equal to or less than 0.4 is used as the second sacrificial layer 140.

A planarization operation, such as, an etch-back process or CMP, may be performed to planarize the upper surface of the second sacrificial layer 140. By the planarization operation, the upper surface of the gate cap layer 132 is exposed. After the planarization operation, the height H_(sacr) of the second sacrificial layer measured from the surface of the first insulating layer 122 is in a range from about 100 nm to about 350 nm in some embodiments.

Then, as shown in FIGS. 16A-16C, after the second sacrificial layer 140 is formed, a mask pattern is formed over the second sacrificial layer 140, and by using the mask pattern as an etching mask, the second sacrificial layer 140 is patterned by using dry etching, thereby forming openings 144 between the S/D structures 120 and 121. In some embodiments, the etching substantially stops at the first insulating layer 122. FIGS. 16A-16C show structure after the mask layer is removed.

The mask pattern may be formed by patterning a layer of suitable mask material using a photo-etching operation. The etching operation may include multiple etching processes using different plasma gases. In some embodiments, the mask pattern extends in the X direction over the second sacrificial layer 140 and the gate cap layer 132. The mask pattern is made of one or more layers of dielectric material, such as SiO₂, SiN and/or SiON, and/or TiN, or other suitable materials. The material for the mask pattern may be deposited through one or more processes such as PVD, CVD, or ALD, although any acceptable process may be utilized. Other materials and/or processes may be used.

When a Si based material (e.g., poly-Si or amorphous Si) is used as the second sacrificial layer 140, the etching can be performed by plasma dry etching using, for example, a gas including HBr or a gas including Cl₂ and SF₆. When SOC (spin-on-carbon) is used as the second sacrificial layer 140, the etching can be performed by plasma dry etching using, for example, a gas including N₂ and H₂ or a gas including SO₂ and O₂. When a Si oxide based material formed by FCVD is used as the second sacrificial layer, the etching can be performed by plasma dry etching using, for example, a gas including a fluorocarbon and/or fluorine.

When a Ge based material (e.g., Ge or SiGe) is used as the second sacrificial layer 140, the etching can be performed by plasma dry etching using, for example, a gas including a fluorocarbon or a gas including a halogen. During the etching, the substrate may be heated at a temperature between about 20° C. to about 200° C.

In some embodiments, the opening width W_(SP) in the Y direction is in a range from about 5 nm to about 100 nm. In certain embodiments, the opening width W_(SP) is in a range from about 10 nm to about 40 nm. The width W_(SP) may be other values depending on design rules and/or types of semiconductor devices.

It is noted that as shown in FIGS. 16A and 16C, the first insulating layer 122 and/or the gate cap layer 132 are not substantially etched during the patterning of the second sacrificial layer 140 in some embodiments. In other words, the materials for the first insulating layer 122 and/or the gate cap layer 132 have a high etching selectivity (e.g., 5 or more) with respect to the second sacrificial layer 140 (i.e., lower etching rate than the second sacrificial layer).

Subsequently, as shown in FIGS. 17A-17C, a second insulating layer 146, as a liner layer, is conformally formed over the patterned second sacrificial layer 140 and the isolation insulating layer 105. The second insulating layer 146 is also formed on the sidewall spacers 134 and the gate cap layer 132.

In some embodiments, the second insulating layer 146 includes SiO₂, SiCN, SiON, SiCN, SiOCN and SiN, but other suitable dielectric materials may be used. In one embodiment, silicon nitride based dielectric material, such as SiN, is used. The second insulating layer 146 may be made of a plurality of layers that comprises combinations of the above mentioned materials. In one embodiment, two layers of silicon based dielectric material, at least one of which is silicon nitride based material, are used as the second insulating layer 146. In other embodiments, an aluminum based dielectric layer is used as one layer of the second insulating layer 146. In certain embodiments, the second insulating layer 146 includes a silicon nitride based dielectric layer and a dielectric layer made of a material other than a silicon nitride based material.

The second insulating layer 146 has a higher selective etching ratio to silicon compared to the etching rate of SiO₂ to silicon. For example, the etching rates of silicon nitride, silicon oxide, and silicon in H₃PO₄ are respectively about 50:5:1.

The second insulating layer 146 may be deposited through one or more processes such as PVD, CVD, molecular layer deposition (MLD) or ALD, although any acceptable process may be utilized. Other materials and/or processes may be used. In the case of ALD, for example, SiH₄ (silane), SiH₂Cl₂ (dichlorosilane), and/or SiCl₄ (silicon tetrachloride), and/or other suitable silicon-containing precursor for the nitride-containing liner layer may be used as precursor for ALD process.

In some embodiments, the deposition temperature of the second insulating layer 146 is maintained below about 500° C. In other embodiments, the temperature is below about 400° C. The temperature is maintained low to minimize thermal impact on the threshold voltage of the metal-gate/high-k dielectric stack that has already been formed.

In some embodiments, the second insulating layer 146 has a thickness between about 1 nm and about 15 nm. In other embodiments, the thickness is about 3 nm to about 10 nm. Other thicknesses are used in other embodiments.

After the second insulating layer 146 is formed, a first interlayer dielectric (ILD) layer 145 is formed to fill the openings 144 and over the second sacrificial layer 140.

The ILD layer 145 may include a single layer or multiple layers. In some embodiments, the ILD layer 145 includes SiO₂, SiCN, SiOC, SiON, SiOCN, SiN or a low-k material, but other suitable dielectric film may be used. The ILD layer 145 may be formed by CVD, PECVD or ALD, FCVD, or a spin-on-glass process. A planarization process, such as a CMP process, may be performed to remove excess materials. By the planarization process, the upper surface of the second sacrificial layer 140 (and the cap insulation layer 132) is exposed in some embodiments.

When a FCVD is used, a curing process is performed on the flowable isolation dielectric precursor in some embodiments. The curing process may include UV curing, ozone (O₃) plasma curing or low-temperature O₃ plasma+UV curing (LTB+UV curing), so as to transfer the flowable isolation dielectric precursor into the dielectric layer such as silicon oxide layer. A processing temperature range of the UV curing process is between about 0° C. and about 10° C., in some embodiments. A processing temperature range of the O₃ plasma curing process is between about 100° C. and about 250° C. in some embodiments. A processing temperature range of the LTB+UV curing process is between about 30° C. and about 50° C., in some embodiments. The curing process may be performed only one time after the deposition process to reduce the process time, but not limited thereto, in some embodiments. The deposition process and the curing process can be alternately performed. In other embodiments, the flowable isolation dielectric precursor can also be directly transferred into the dielectric layer through an oxidation process by directly introducing nitrogen, oxygen, ozone or steam.

In order to further increase the structural density of the ILD layer, after the curing process, a thermal treatment process may be performed on the isolation dielectric layer. The thermal treatment process includes a steam containing thermal treatment process (wet annealing) and a nitrogen-containing thermal treatment process (dry annealing). A processing temperature range of the steam-containing thermal treatment is between about 400° C. and about 1000° C., in some embodiments, and the processing temperature of the nitrogen-containing thermal treatment process is between about 1000° C. and about 1200° C. In other embodiments, the temperature of thermal treatment can be reduced to about 400° C. by exposing the film to ultra-violet radiation, e.g., in a ultra-violet thermal processing (UVTP) process.

After the curing or treatment, the ILD layer may have a relative permittivity of less than 6, in some embodiments.

In other embodiments, a spin on dielectric (SOD) process is performed to form the ILD layer 145. In this embodiment, the second insulating layer 146, a nitride-containing liner layer, is formed in the prior process to provide a suitable inter layer to the deposited isolation dielectric layer in contact isolation region by SOD process. Therefore, the ILD layer may be formed by the SOD process using suitable precursor.

In the SOD process for the ILD layer 145, the precursor may be organosilicon compounds, such as but not limited to siloxane, methylsiloxane, polysilazane and hydrogensilsesquioxane, perhydropolysilazane (PHPS), and other suitable materials. The SOD precursor is dissolved in a compatible organic solvent commonly used in coating solutions of spin-on chemicals. Suitable organic solvents include, for example, dibutyl ether (DBE), toluene, xylene, propyleneglycolmonomethyletheracetate (PGMEA), ethyl lactate and isopropyl alcohol (IPA), and the like, preferably use xylene as the solvent for PHPS. The concentration of the SOD precursor in solution can be varied to adjust the consistency (i.e., viscosity) of the solution and thickness of the coating. A solution containing between about 4% to about 30% by weight of SOD precursor can be used, in some embodiments. In other embodiments, a solution containing about 8% to about 20% by weight SOD precursor is used. Additional minor amounts of additives such as surfactants and binders can be included in the solution.

The wafer is spun to uniformly spread SOD precursor from wafer center to edge during precursor spin-on process. The spin speed of cast rotation for SOD precursor coating on substrate is from 100 rpm to 3000 rpm, in some embodiments, for a 12 inch wafer. The dynamic dispense rate of SOD precursor is around 1 ml/sec in some embodiments, and the dispense puddle will spread completely to the edge of the wafer before main speed. The SOD precursor can therefore totally cover the bottom of contact isolation hole and fill the opening 144.

Subsequently, a prebaking process is performed after SOD deposition to stablize the SOD layer. The prebaking process is performed at low temperature in a range of about 100° C. to about 200° C. in air ambient, in some embodiments. A thermal treatment process is performed after prebaking process to densify the SOD layer. The thermal treatment process is an annealing process performed at high temperature in a range of about 400° C. to about 1100° C., in some embodiments. The annealing process may be a wet annealing process using a gas including steam, O₂ and H₂ gas or a dry annealing process using a gas including N₂ and O₂ gas. In the other embodiments, the thermal treatment process uses plasma at a lower temperature in a range of about 150° C. to about 400° C. The partial pressure ratio of water vapor (H₂O) to hydrogen (H₂) preferably is controlled to a value in a range of about 1×10⁻¹¹ to about 1.55.

Subsequently, as shown in FIGS. 18A-18D, the second sacrificial layer 140 is removed, thereby forming contact openings 148 and 149 to expose the S/D structures 120, 121 covered by the first insulating layer 122. The etching operation to remove the second sacrificial layer 140 may be isotropic or anisotropic. In addition, the first insulating layer 122 is removed, thereby exposing the S/D structures 120, 121.

When a Si based material (e.g., poly-Si or amorphous Si) is used as the second sacrificial layer 140, the etching can be performed by plasma dry etching using a gas including Cl₂ and NF₃ or a gas including F₂, or wet etching using NH₄OH and/or tetramethylammonium (TMAH). When SOC (spin-on-carbon) is used as the second sacrificial layer 140, the etching can be performed by plasma dry etching using, for example, a gas including N₂ and H₂ or a gas including SO₂ and O₂. When a Si oxide based material formed by FCVD is used as the second sacrificial layer, the etching can be performed by wet etching using, for example, HF or buffered HF (BHF).

When a Ge based material (e.g., Ge or SiGe) is used as the second sacrificial layer 140, the etching can be performed by plasma dry etching using, for example, ozone, or wet etching using a solution containing NH₄OH and H₂O₂ or a solution containing HCl and H₂O₂.

The remaining first insulating layer 122 can be removed by using a suitable etching operation. In some embodiments, during the etching of the first insulating layer 122, the second insulating layer 146 is also etched when the second insulating layer 146 is made of the same or similar material as the second insulating layer 122. In certain embodiments, the second insulating layer 146 is fully removed from the wall of the contact openings 148 and 149. However, even in such a case, the second insulating layer 146 remains at the bottom of the ILD layer 145 in some embodiments.

Since the etching rate for the second sacrificial layer 140 is higher than other materials, it is possible to remove the second sacrificial layer 140 without causing damage in the other layers, for example, the gate cap layer 132, the sidewall spacers 134, the first insulating layer 122, the ILD layer 145 and/or the second insulating layer 146.

The width W_(CH) along the Y direction of the openings 148, 149 is in a range from about 10 nm to about 100 nm in some embodiments. In other embodiments, the width W_(CH) is in a range from about 15 nm to about 50 nm.

After the second sacrificial layer and the first insulating layer 122 formed on the S/D structures 120, 121 are removed, a conductive material is filled in the contact openings 148, 149, thereby forming S/D contacts 150, as shown in FIGS. 19A-19C.

In some embodiments, a silicide layer 127 is formed on the exposed S/D structures 120, 121. The metal silicide formation process may form a metal silicide on the side portions of the S/D structures. The metal silicide formation process includes a metal film deposition on the S/D structures, a thermal treatment to form a metal silicide at the interface or surface of the S/D structures, and an etching process to remove the excess unreacted metal. The metal silicide comprises TiSi_(x), NiSi_(x), CoSi_(x), NiCoSi_(x), and TaSi_(x), but other suitable silicide materials may be used. In some embodiments, the silicide layer has a thickness between about 0.5 nm and about 10 nm. In other embodiments, a silicide layer is not formed at this stage of the manufacturing operations, and may be formed at an earlier manufacturing stage, e.g., before forming the first insulating layer 122. In some embodiments, a metal film is also formed on the second insulating layer 146 and the isolation insulating layer 105. The metal films not formed on the S/D epitaxial layer and the metal films not consumed to form the silicide layer are removed by a suitable etching operation in some embodiments. In other embodiments, the metal films are not removed and remain.

The S/D contacts 150 may include a single layer or a multi-layer structure. For example, in some embodiments, the contact 150 includes a contact liner layer, such as a diffusion barrier layer, an adhesion layer, or the like, and a contact body formed over the contact liner layer in the contact openings 148, 149. The contact liner layer may include Ti, TiN, Ta, TaN, or the like formed by ALD, CVD, or the like. The contact body may be formed by depositing a conductive material, such as one or more layers of Ni, Ta, TaN, W, Co, Ti, TiN, Al, Cu, Au, alloys thereof, combinations thereof, or the like, but other suitable metals may also be used. A planarization process, such as a CMP, may be performed to remove excess material from a surface of the ILD layer 145.

After the S/D contact 150 is formed, the height H_(g) of the gate structure including the gate cap layer 132 measured from the top of the fin structure 102 is in a range from about 20 nm to 100 nm and the height of the metal gate 130 measured from the top of the fin structure 102 is in a range from about 10 nm to about 60 nm in some embodiments.

After forming the contact 150, further CMOS processes are performed to form various features such as additional interlayer dielectric layers, contacts/vias, interconnect metal layers, and passivation layers, etc.

As set forth above, after the S/D structure 120 is formed, various operations including film formation operations are performed. Some of the subsequent operations require heating operations, and some of the heating operations require higher temperature such as 700° C. or more (and 1200° C. or less). If Ge and/or Sn is not included in the S/D structure 120 (e.g., SiP or SiAs) for an n-type FET, deactivation of P (or As) would occur. However, in the foregoing embodiments, since Ge and/or Sn is included in the S/D structure 120 (e.g., SiP) for the n-type FET, deactivation of P (or As) can be suppressed, and thus a higher number of activated phosphorous (or arsenic) can be obtained.

FIGS. 20A-22C illustrate various processes in a semiconductor device fabrication process in accordance with other embodiments of the present disclosure. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements. In FIGS. 20A-22C, the “A” figures (e.g., FIGS. 20A, 21A, etc.) illustrate a perspective view, the “B” figures (e.g., FIGS. 20B, 21B, etc.) illustrate a cross-sectional view along the Y direction corresponding to line Y1-Y1 illustrated in FIG. 3A, and the “C” figures (e.g., FIG. 20C, 21C, etc.) illustrate a cross-sectional view along the X direction corresponding to line X1-X1 illustrated in FIG. 3A. It is understood that additional operations can be provided before, during, and after processes shown by FIGS. 20A-22C, and some of the operations described below can be replaced or eliminated, for additional embodiments of the method. The order of the operations/processes may be interchangeable. Material, configuration, dimensions and/or processes the same as or similar to the foregoing embodiments described with respect to FIGS. 1A-19C may be employed in the following embodiments, and detailed explanation thereof may be omitted.

After the structure shown in FIGS. 13A-13C is formed, the first sacrificial layer 115, which is used as a first interlayer dielectric layer in this embodiment, is patterned to form contact openings 148′ and 149′, as shown in FIGS. 20A-20C. One or more lithography and etching operations are employed to form the contact openings 148′ and 149′.

Similar to the operation explained with FIGS. 19A-19C, a silicide layer 127 is formed on the exposed S/D structures 120, 121. The conductive material layer 150 is formed in the openings 148′ and 149′ and the ILD layer 115, as shown in FIGS. 21A-21C. The conductive material layer for the S/D contacts 150 may include a single layer or a multi-layer structure. A planarization process, such as a CMP, may be performed to remove excess material from a surface of the ILD layer 145, as shown in FIGS. 22A-22C.

After forming the contact 150, further CMOS processes are performed to form various features such as additional interlayer dielectric layers, contacts/vias, interconnect metal layers, and passivation layers, etc.

It will be understood that not all advantages have been necessarily discussed herein, no particular advantage is required for all embodiments or examples, and other embodiments or examples may offer different advantages.

For example, in the present disclosure, by containing Ge and/or Sn in an epitaxial source/drain structure for an n-type FET, it is possible to suppress de-activation of the P and/or As in the epitaxial source/drain structure, thereby improving contact resistance between the epitaxial source/drain structure and the source/drain metal contact.

In accordance with an aspect of the present disclosure, a semiconductor device includes a field effect transistor (FET). The FET includes a channel region and a source/drain region disposed adjacent to the channel region, and a gate electrode disposed over the channel region. The FET is an n-type FET, and the channel region is made of Si. The source/drain region includes an epitaxial layer including Si_(1-x-y)M1_(x)M2_(y), where M1 is one or more of Ge and Sn, and M2 is one or more of P and As, and 0.01≤x≤0.1. In one or more of the foregoing or following embodiments, M1 is Ge. In one or more of the foregoing or following embodiments, M2 is P. In one or more of the foregoing or following embodiments, 0.01≤x≤0.05. In one or more of the foregoing or following embodiments, 0.01≤y≤0.1. In one or more of the foregoing or following embodiments, M1 is Ge and a concentration of Ge decreases from an outer surface of the epitaxial layer toward inside the epitaxial layer.

In accordance with another aspect of the present disclosure, a semiconductor device includes fin field effect transistors (FinFETs). The semiconductor device includes an n-type FinFET and a p-type FinFET. The n-type FinFET includes a first fin structure, a first source/drain structure and a first source/drain contact in contact with the first source/drain structure. The p-type FinFET includes a second fin structure, a second source/drain structure and a second source/drain contact in contact with the second source/drain structure. The first source/drain structure includes a first epitaxial layer including Si_(1-x-y)M1_(x)M2_(y), where M1 is one or more of Ge and Sn, and M2 is one or more of P and As, and 0.01≤x≤0.1. In one or more of the foregoing or following embodiments, M1 is Ge. In one or more of the foregoing or following embodiments, M2 is P. In one or more of the foregoing or following embodiments, 0.01≤x≤0.05. In one or more of the foregoing or following embodiments, 0.01≤y≤0.1. In one or more of the foregoing or following embodiments, the second source/drain structure includes a second epitaxial layer including SiGe or Ge. In one or more of the foregoing or following embodiments, the second epitaxial layer further includes boron. In one or more of the foregoing or following embodiments, M1 is Ge and a concentration of Ge increases from a region adjacent to the first fin structure to a region adjacent to an outer surface of the first epitaxial layer. In one or more of the foregoing or following embodiments, the concentration of Ge continuously increases. In one or more of the foregoing or following embodiments, the concentration of Ge increases in a stepwise manner. In one or more of the foregoing or following embodiments, the semiconductor device further includes a dielectric layer separating the first source/drain structure and the second source/drain structure. The dielectric layer is made of silicon-based insulating material, and contains Ge at or near an interface between the dielectric layer and one of the first and second source/drain contacts. In one or more of the foregoing or following embodiments, the second source/drain structure includes a second epitaxial layer, the first epitaxial layer wraps around a source/drain region of the first fin structure, and the second epitaxial layer wraps around a source/drain region of the second fin structure. In one or more of the foregoing or following embodiments, the first source/drain contact wraps around the first epitaxial layer, and the second source/drain contact wraps around the second epitaxial layer.

In accordance with another aspect of the present disclosure, in a method of fouling a semiconductor device including a fin field effect transistor (FinFET), a first sacrificial layer is formed over a source/drain structure of a FinFET structure and an isolation insulating layer. The first sacrificial layer is patterned, thereby forming an opening. The first liner layer is formed on the isolation insulating layer in a bottom of the opening and on at least side faces of the patterned first sacrificial layer. After the first liner layer is formed, a dielectric layer is formed in the opening. After the dielectric layer is formed, the patterned first sacrificial layer is removed, thereby forming a contact opening over the source/drain structure. A conductive layer is formed in the contact opening. The FinFET is an n-type FET, and the source/drain structure includes an epitaxial layer including Si_(1-x-y)M1_(x)M2_(y), where M1 is one or more of Ge and Sn, and M2 is one or more of P and As, and 0.01≤x≤0.1.

The foregoing outlines features of several embodiments or examples so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments or examples introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. 

What is claimed is:
 1. A semiconductor device including a field effect transistor (FET), the FET comprising: a channel region and a source/drain region disposed adjacent to the channel region; and a gate electrode disposed over the channel region, wherein: the FET is an n-type FET, the channel region is made of Si, and the source/drain region includes an epitaxial layer including Si_(1-x-y)M1_(x)M2_(y), where M1 includes Sn, M2 is one or more of P and As, 0.01≤x≤0.1, and 0.01≤y≤0.1.
 2. The semiconductor device of claim 1, wherein M1 further includes Ge.
 3. The semiconductor device of claim 2, wherein M2 is P.
 4. The semiconductor device of claim 1, wherein a concentration of M1 is in a range from about 0.5×10²¹ cm⁻³ to about 4.0×10²¹ cm⁻³.
 5. The semiconductor device of claim 1, wherein M1 includes Ge and a concentration of Ge decreases from an outer surface of the epitaxial layer toward inside the epitaxial layer.
 6. A semiconductor device including fin field effect transistors (FinFETs), comprising: an n-type FinFET including a first fin structure, a first source/drain structure and a first source/drain contact in contact with the first source/drain structure; a p-type FinFET including a second fin structure, a second source/drain structure and a second source/drain contact in contact with the second source/drain structure, wherein: the first source/drain structure includes a first epitaxial layer including Si_(1-x-y)M1_(x)M2_(y), where M1 includes Sn, M2 is one or more of P and As, 0.01≤x≤0.1, and 0.01≤y≤0.1.
 7. The semiconductor device of claim 6, wherein M1 further includes Ge.
 8. The semiconductor device of claim 7, wherein M2 is P.
 9. The semiconductor device of claim 6, wherein a concentration of M1 is in a range from about 0.5×10²¹ cm⁻³ to about 4.0×10²¹ cm⁻³.
 10. The semiconductor device of claim 6, wherein the second source/drain structure includes a second epitaxial layer including SiGe or Ge.
 11. The semiconductor device of claim 10, wherein the second epitaxial layer further includes boron.
 12. The semiconductor device of claim 6, wherein M1 includes Ge and a concentration of Ge increases from a region adjacent to the first fin structure to a region adjacent to an outer surface of the first epitaxial layer.
 13. The semiconductor device of claim 12, wherein the concentration of Ge continuously increases.
 14. The semiconductor device of claim 12, wherein the concentration of Ge increases in a stepwise manner.
 15. The semiconductor device of claim 6, further comprising: a dielectric layer separating the first source/drain structure and the second source/drain structure, wherein the dielectric layer is made of silicon-based insulating material containing Ge, and the Ge is at or near an interface between the dielectric layer and one of the first and second source/drain contacts.
 16. The semiconductor device of claim 6, wherein: the second source/drain structure includes a second epitaxial layer, the first epitaxial layer wraps around a first source/drain region of the first fin structure, and the second epitaxial layer wraps around a second source/drain region of the second fin structure.
 17. The semiconductor device of claim 16, wherein: the first source/drain contact wraps around the first epitaxial layer, and the second source/drain contact wraps around the second epitaxial layer.
 18. A semiconductor device including a fin field effect transistor (Fin FET), the Fin FET comprising: a fin structure having a channel region and a source/drain region; and a gate electrode disposed over the channel region, wherein: the FET is an n-type FET, and the source/drain region includes an epitaxial layer made of Si_(1-y-a-b)Ge_(a)Sn_(b)M2_(y), wherein 0<a, 0<b, 0.01≤(a+b)≤0.1, 0.01≤y≤0.1, and M2 is P or As.
 19. The semiconductor device of claim 18, wherein a concentration of Ge and Sn is in a range from about 0.5×10²¹ cm⁻³ to about 4.0×10²¹ cm⁻³.
 20. The semiconductor device of claim 19, wherein M2 is P. 